1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to a memory circuit for reading and writing a memory array including redundant columns.
2. Description of the Related Art
It is common practice for the manufacturers of memory chips to test the functionality of the memories at the manufacturing site. Before the memory chips are released for shipment, they typically undergo testing to verify that each of the memory cells within the memory array is functioning properly. This testing method is routinely performed because it is not uncommon for a percentage of the memory cells within the chip to fail, either because of manufacturing defects or degradation faults.
Because of this likelihood of failing cells, memory arrays are typically manufactured with redundant rows or columns. When failing rows or columns are detected during manufacturing testing, these locations may be permanently disabled and accesses to these cells are instead routed to cells of a redundant row or column. This procedure increases chip yields while maintaining high test coverage.
Turning now to FIG. 1, a block diagram of portions of a typical memory system including redundant columns is depicted. As shown, static RAM (SRAM) memory device 10 includes column n switch logic 20A, column (n+1) switch logic 20B, and sense amplifier 50. Column n switch logic 20A includes a bit line 22A coupled to a transmission gate 24A. Although not shown in FIG. 1 for simplicity, bit line 22A is also coupled to a column of SRAM memory cells within SRAM memory device 10. The n-channel transistor of transmission gate 24A is coupled to a column n repair signal 28A, while the p-channel transistor of transmission gate 24A is coupled to an inverted column n repair signal 28A. Transmission gate 24A is also coupled to a transmission gate 26A a bit line recover logic block 44A, a column n read transistor 40A, and a column n write transistor 42A. Inverted column n repair signal 28A is also coupled to the n-channel transistor of transmission gate 26A, while the p-channel transistor of transmission gate 26A is coupled to non-inverted column n repair signal 28A. Transmission gate 26A is additionally coupled to bit line 30A which is correspondingly coupled to a column (n+2) of memory cells within SRAM memory device 10.
Column n read transistor 40A is further coupled to sense amplifier 50 via a sense amplifier read input 38A, and receives an inverted version of column n read select signal 32A as a selection signal. Column n write transistor 42A receives a write data bit n 36A as input, and column n write select signal 34A for selection control.
Column (n+1) switch logic 20B is configured similarly to column n switch logic 20A. Column (n+1) switch logic 20B includes a bit line 22B, a transmission gate 24B, a transmission gate 26B, a column (n+1) repair signal 28B, a bit line recover logic block 44B, a column (n+1) read select signal 32B, a column (n+1) write select signal 34B, a column (n+1) read transistor 40B, a column (n+1) write transistor 42B, a write data bit (n+1) 36B, and a sense amplifier read input 38B.
Although not shown in FIG. 1, column n switch logic 20A and column (n+1) switch logic 20B each include a bit line complement signal (with associated transmission gates and read/write transistors). During read and write operations, this bit line carries the complement of the value conveyed on the regular bit line.
Column n switch logic 20A is configured to route read and write data as specified by column n repair signal 28A. For a read operation, column n read select signal 32A is asserted, causing column n read transistor 40A to be activated. A bit value will then be conveyed to sense amplifier 50 from either bit line 22A or bit line 30A, depending on the state of column n repair signal 28A. If column n repair signal 28A is active, the bit value on bit line 22A is conveyed to sense amplifier read input 38A. If column n repair signal 28A is inactive, the bit value on bit line 30A is conveyed to sense amplifier read input 38A.
The assertion of column n repair signal 28A indicates that no failing columns have been detected prior to and including column n within SRAM memory device 10. The read value conveyed to sense amplifier read input 38A thus corresponds to the bit line 22A of column n. The terms "prior to" and "subsequent to" are used herein to refer to relative column positions within a memory array. A first column is prior to a second column if the first column receives a more significant bit than the second column during a write operation (assuming an initial column in the array receives the most significant bit in a write operation). Accordingly, a first column is subsequent to a second column if the second column receives a more significant bit during a write operation. If column n repair signal 28A is de-asserted, this indicates that either column n has failed or that a column prior to column n has failed. The read value conveyed to sense amplifier read input 38A is thus conveyed from a bit line from a subsequent column (e.g., bit line 30A from column (n+2)).
A write operation proceeds similarly. In column switch logic 20A, column n write select signal 34A activates column n write transistor 42A, driving write data bit n 36A to one of two bit lines. Write data bit n 36A is conveyed to bit line 22A through transmission gate 24A if column n repair signal 28A is asserted, and is conveyed to bit line 30A through transmission gate 26A if column n repair signal 28A is de-asserted. If column n repair signal 28A is de-asserted, a data bit (n-2) may be routed to bit line 22A through a transmission gate not shown in FIG. 1.
Thus, to perform a read operation, the read data (from bit line 22A or 22B) passes through transmission gate 24A and column n read transistor 40A. Similarly, to write data to bit line 22A, write data bit m 36A passes through both column n write transistor 42A and transmission gate 24A. The speed of SRAM device 10 for read/write operations is thus limited by this transmission gate/transistor path.
As described above, each column in SRAM device 10 includes both a bit line and a bit line complement signal. During a write operation, one of these signals is driven to a logic low level. Before a subsequent access takes place, each of these signals is precharged to a logic high voltage by bit line recover logic 44. This precharge time, or "write recovery time", increases as the loading on the bit lines increases. Increased write recovery time results in more idle time between successive write operations, and slower overall operation of SRAM device 10.
A memory circuit is therefore desirable which may attain increased read/write speed and reduced loading upon each of the bit lines.